Esterel Technologies Develops Top-Level Validation Methodology for STMicroelectronics
Speeds Functional Verification of Chips with Multiple Design Blocks
MOUNTAIN VIEW, Calif. and GUYANCOURT, France--(BUSINESS WIRE)--
June 24, 2002--
STMicroelectronics Is First Customer to Tape Out After Using Esterel
Studio to Create Top-Level Validation Test Suite for New Generation of
Embedded Communications SoCs
Esterel Technologies today announced it has developed a new
methodology for automating the generation of a top-level validation
test suite for system-on-chip (SoC) designs.
The methodology, when used with Esterel Studio 4.0, speeds the
validation of design block and CPU core integration by relying on
transactional models that describe blocks according to their services
(such as read/write) rather than their individual signals.
Esterel Technologies also announced today that STMicroelectronics
will be the first customer to have taped out a design after applying
top-level validation. The chip is a new multiple-block design for the
digital consumer market. Using Esterel Studio 4.0 and the top-level
validation methodology, STMicroelectronics generated more than 1,200
test cases for their new SoCs in a week. Using hand coding, fewer than
10 test cases could have been generated in the same period. As a
result of this new methodology, STMicroelectronics will be able to
tape out its new SoC with a high degree of confidence that design
block and CPU core interaction has been thoroughly validated.
"We needed a solution to help us build and verify critical parts
of our embedded SoC for digital consumer applications, and we knew
from past experience that Esterel Technologies had proven verification
tools," said Jean-March Chateau, director of design for Consumer and
Microcontroller Groups at STMicroelectronics. "The top-level
validation solution has significantly streamlined the development of
our next-generation SoCs. We automatically generated the new test
suite three to five times faster than our previously hand-coded
suites."
"Verification is the major bottleneck of SoC design today," said
Eric Bantegnie, president and CEO of Esterel Technologies. "Industry
sources confirm that verifying a design consumes up to 70% of overall
SoC design time. To combat this, most SoC designers follow a
traditional 'divide and conquer' test strategy. They verify each
design block individually and separately, and then verify the
interaction of the design blocks on the chip."
Bantegnie added, "Nothing is wrong with this strategy, but it's
all been done by hand and is very time consuming. Now, with the
benefit of our automated tools and top-level validation methodology,
system architects can quickly define the functional capabilities of an
architecture and construct a validation test suite that describes what
should be tested. Then the verification team can easily perform the
system-level functional tests to fully validate the interconnections
and interactions of the design blocks, CPU cores, and custom blocks."
The methodology involves using Esterel Studio to write the
transactional models (using knowledge of the SoC architecture and the
specification documents), create a top-level validation model that
integrates all the transactional models in parallel, and then generate
the top-level validation test suite. Using the customer's simulation
platform, engineers then run the validation test suite.
Unlike random and directed test suite generation methods, the
automatically produced test suite is efficient at covering concurrent
behaviors of SoC internal blocks and at reaching corner cases. Esterel
Studio's test suite generation engine is capable of producing a
minimal size testbench reaching 100% state and transition coverage of
the original transactional model.
About Esterel Studio 4.0
Esterel Studio 4.0 automatically generates a top-level validation
test suite in C or C++. It also includes a gateway to ModelSim(TM),
one of the most widely used simulators in the EDA market; and to
CoWare N2C(TM). As a result, Esterel Studio 4.0 can validate all
possible meaningful source code states and transitions, ensuring
comprehensive code validation of an entire SoC design.
About Esterel Technologies
Esterel Technologies provides electronic system and embedded
software designers with methodologies and tools that improve their
productivity and remove the barriers between system specification,
implementation and validation. The company's products automate costly
and time-consuming coding and validation work through executable
specification, intelligent test suite generation and automatic code
generation. Esterel Technologies is an international company with
offices in France, Germany, U.K. and the United States. For more
information: www.esterel-technologies.com
Contact:
Esterel Technologies
Hassan Laasri, +33-1-30-68-61-73
hassan.laasri@esterel-technologies.com
or
Cayenne Communication
Michelle Clancy, 252/940-0981
michelle.clancy@cayennecom.com
